1. Field of the invention
The present invention relates to a nonvolatile memory device and a method for fabricating the same and, more particularly, to a nonvolatile memory device with nanowire channel and a method for fabricating the same.
2. Description of Related art
General nonvolatile memory devices can make use of multiple-gate structure and ultra-thin channel to enhance the control capability over channel in order to increase data writing/erasing efficiency. FinFETs and nanowire FETs are common selections. In ordinary industrial circles, however, it is usually necessary to use E-beam and silicon on insulator (SOI) wafer material for the fabrication of ultra-thin channel devices. Therefore, both the cost and the technology threshold are high. In addition, general academic circles fabricate nanowire in a bottom-up manner. Although the cost is not high, there exist the problems of reproducibility, reliability and mass production. Moreover, when fabricating FETs, it is difficult to align electrode and nanowire. Therefore, there are many improvements to be made in practical application.
For instance, Taiwan Pat. No. 1,246,541 discloses a fabrication method of low-cost and mass producible silicon nanowire, in which a silicon substrate is catalyzed by sensitizer and activator so that reacting metal atoms can be adsorbed on the surface of the silicon substrate. The processed silicon substrate is then dipped in an acidic electroless plating solution for electroless deposition in order to form a metal layer containing catalytic metal particles on the silicon substrate. Next, this silicon substrate is heated in a tubular oven to catalyze metal particles and silicon atoms on the surface of the silicon substrate to form liquid silicide alloy at the metal/silicon interface. Subsequently, a solid-liquid-solid (SLS) chemical synthesis process prompts rearrangement of silicon-silicon bonds due to catalyst effect through temperature gradient so as to form silicon nanowire by stacking. Although this disclosure can mass produce silicon nanowire, the problem of alignment will still be encountered when fabricating FETs. Moreover, there is doubt of contamination by residual catalytic metal.
In the paper “FinFET SONOS flash memory for embedded applications” disclosed by P. Xuan et al. in 2003, the thickness of a silicon film is reduced from 100 nm to 40 nm on a fully-depleted (FD)-SOI wafer by means of thermal oxidation and etching, and a fin-shaped channel is then defined by means of E-beam lithography. Next, a silicon oxide film, a silicon nitride film and a silicon oxide film are grown in turn to form a gate dielectric stack structure of oxide/nitride/oxide (ONO). Subsequently, an n-type poly-Si film is deposited, and a gate is defined by means of E-beam lithography so as to form a FinFET SONOS memory device. However, advanced techniques and expensive SOI wafer and E-beam lithography equipments are required in these process steps.
In the paper “Nonvolatile memory and programmable logic from molecule-gated nanowires” disclosed by X. Duan et al. in 2002, a nanowire metal seed is used as the medium for the fabrication of nanowires, and nanowires are then sprayed on a silicon wafer covered by an insulator. Next, metal electrodes are formed by means of E-beam evaporation, and the positions of electrodes are defined by means of E-beam lithography so that the electrodes can be connected with nanowires to finish the fabrication of an FET with nanowire channel. However, the reproducibility of devices fabricated in this manner is low, and there is doubt of residual metal seed in nanowires. Moreover, there exists the problem of accurate alignment of nanowires on the wafer.